1. Field of the Invention
The present invention relates to a circuit for controlling a clock signal, and more particularly, to a circuit for controlling a variation in the frequency of a clock signal, which is capable of controlling an unwanted and abrupt variation in the frequency of a clock signal.
2. Description of the Related Art
In general, a clock signal is used for synchronization within a system or between systems, and various devices are designed to perform a process based on a clock signal.
When an abrupt variation in the frequency of a received clock signal is generated, the system does not perform an internal process or an error is generated in the system.
A system using a clock signal may be, for example, a Liquid Crystal Display (LCD). The timing controller of the LCD is one of representative devices for receiving an external clock signal and performing a process based on the clock signal.
A clock signal may include, for example, a clean clock signal and a Spread Spectrum Clock (hereinafter referred to as ‘SSC’) signal. A clean clock signal refers to a clock signal whose frequency remains constant, and an SSC signal refers to a clock signal whose frequency varies over time in order to reduce electromagnetic interference (EMI). A system using such a clean clock signal or an SSC signal may not perform a normal process when an unwanted and abrupt variation is generated in the frequency of a received clock signal.
FIG. 1(a) illustrates an abrupt variation in the frequency of a clean clock signal, and FIG. 1(b) illustrates an abrupt variation in the frequency of an SSC signal.
FIG. 1(a) shows a frequency variation over time when an unwanted and abrupt frequency variation, such as “A1”, is generated in a clean clock signal used in a system due to an unspecified external or internal influence.
FIG. 1(b) shows a frequency variation over time when an unwanted and abrupt frequency variation, such as “A2”, is generated in an SSC signal used in a system due to an unspecified external or internal influence.
The causes of unwanted and abrupt variations in the frequency, such as “A1” and “A2” of FIGS. 1(a) and 1(b), may include EMI due to an external circuit, power noise, ground noise, and noise within a chip.
In a system in which a clean clock signal or an SSC signal is synchronized with data or another clock signal, an abrupt variation in the frequency of the clean clock signal or the SSC signal may not maintain synchronization or may lead to a loss of data. Furthermore, a clean clock signal or an SSC signal having an abrupt frequency variation may deviate from a frequency range that can be received in a system.
Accordingly, if an abrupt variation in the frequency of a clock signal is generated in a conventional system, the system does not normally operate and requires a series of other processing (e.g., the restart of the system) for a normal operation.
In general, an abrupt variation in the frequency of a clean clock signal, such as that of FIG. 1(a), may be removed using a Phase Locked Loop (hereinafter referred to as ‘PLL’). In this case, in order to block the abrupt variation in the frequency of the clean clock signal, the PLL needs to be designed to have a very small loop bandwidth. In order for the PLL to have a very small loop bandwidth, the capacitor of a loop filter needs to have high capacitance. An increase in the capacitance of the capacitor of the loop filter results in an increased chip size. Accordingly, efficiency is low if a PLL is designed to have a very small loop bandwidth in order to block an abrupt variation in the frequency of a clean clock signal.
Furthermore, it is difficult to control an abrupt variation in the frequency of an SSC signal, such as that of FIG. 1(b), by controlling the loop bandwidth of a PLL. The frequency of an SSC signal continues to vary over time. Accordingly, if the PLL is designed to have a very small loop bandwidth, a distributed spectrum characteristic is deteriorated. As a result, the PLL has a limited loop bandwidth attributable to the distributed spectrum characteristic. Accordingly, an abrupt variation in the frequency of the SSC signal cannot be removed by controlling only the loop bandwidth of the PLL.
Accordingly, there is a need for a technique capable of effectively blocking an abrupt variation in the frequency of a clock signal, such as a clean clock signal or an SSC signal used in a system.